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Home > Products > High-Performance and Custom ASIC (SoC) > Advanced Process Technology

Advanced Process Technology

October 25, 2015

Semiconductor processing technology is down to the deep submicron nodes, and volume production of 28nm semiconductors has already started. Socionext is working with Taiwan Semiconductor Manufacturing Company Limited (TSMC) for manufacturing of 40nm process and further. By the synergetic effect of the world's best manufacturing capability of TSMC and the quality-control system and design-engineering ability of Socionext, we will continue to lead the LSI industry in design and manufacture of cutting-edge custom SoCs of 28nm process and beyond.

Product Lineup

Technology Series Power Supply Voltage (Typ.)
7nm FinFET CMOS CS801 series +0.65V±0.065V / +0.75V±0.075V
12nm FinFET CMOS CS661 series + 0.7V± 0.07V / +0.8V± 0.08V
16nm FinFET CMOS SC602 series + 0.7V± 0.07V / +0.8V± 0.08V
28nm Metal Gate CMOS CS407 series +0.8V±0.08V / +0.9V±0.09V
28nm Metal Gate CMOS CS405 series +0.9V±0.09V
40nm Si Gate CMOS CS302 series +1.1V±0.1V
55nm Si Gate CMOS CS251 series +1.2V±0.1V
65nm Si Gate CMOS CS201 series +0.9 V to +1.3 V (supports a wide range)
90 nm Si Gate CMOS CS101 series +0.9 V to +1.3 V (supports a wide range)

 

ASIC - Standard Cell

Standard Cell

The standard cells, by optimizing chip sizes, realize LSIs with higher integration and performance than is possible with macro-embedded cell arrays.

ASIC - Standard Cell

Embedded Array

Macros whose sizes have been optimized at the transistor level can be implemented on gate arrays, enabling high-performance LSIs. A wide range of frames can be offered to the customers.

ASIC - Standard Cell

Gate / Array

Chips where the transistors (basic cells) are regularly placed are prepared. In them, only routing is provided. Thus, gate arrays shorten development time.

gate Scale Comp2020 smallPower Consumption Comp 2020 small

 

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Advanced Front and Back End Technologies
Analog Macros
ARM Core Macros
ASSP-based Development
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Back-end Design
DesignExpress
DFT(Design For Test) Technology
Front-end Design
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High-Performance Subsystems
Interface Macros
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Line-up of IP Macro

Related Documents

CS101 90nm CMOS ASIC Data Sheet
CS201 65nm CMOS ASIC Data Sheet
CS251 55nm CMOS ASIC Data Sheet
CS302 40nm CMOS ASIC Data Sheet
CS402 28nm CMOS ASIC Data Sheet
Custom SoC and ASIC Catalog
Socionext Corporate Profile
Socionext Custom SoC (ASIC) Catalog
Socionext Platform SoC Catalog
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