The demand for reducing the power consumption of LSIs has been getting stronger in recent years. In our SoC design efforts, we are undertaking various initiatives to meet customers' demands for lower power consumption. In order to achieve low power consumption LSIs, it is effective to combine various kinds of technologies as well as using individual technologies. Socionext's design environment "Reference Design Flow" supports various low power consumption technologies and enables the power consumption of LSIs to be reduced during both operation and standby. By controlling the power supply in particular, we develop methodologies for systematically achieving low power consumption. Also, by fully adopting UPF/CPF, we make low power consumption design, easy for customers while minimizing changes to their design assets. The use of UPF/CPF allows for high reliability designs even with low power consumption technology, which it has been extremely difficult to verify in the past.
Multi voltage Design
With this technology, different voltages are supplied to an LSI to reduce power consumption during the operation of circuit blocks for a high-speed operation circuit block, a high voltage is supplied, and for a low-speed operation circuit block, a low voltage is supplied. Using UPF/CPF allows physical design and verification of circuit blocks with different voltages to be performed together, minimizing extension of the development period for low power consumption design.
Clock Gating
Clock gating enables the power consumption of LSIs during operation to be reduced by stopping the supply of clock signals to circuit blocks that do not need to operate.
Power Management
We provide power management technology to control power gating, SRAM sleep, and shut-down mode in a comprehensive manner. By thoroughly eliminating useless, this technology contributes to low power consumption. With its unique power switch controlling system, Socionext's power management technology suppresses the rush current noise generated when the power supply is turned on and off to prevent LSIs from malfunctioning. In addition, using UPF/CPF allows physical design and verification of circuit blocks that have a power shutdown circuit to be performed together, minimizing extension of the development period.
Adaptive Power Supply Control (DVFS*1, AVS*2/ Advanced-AVS)
We can use DVFS, which is for varying the voltage and frequency according to the required throughput. This technology also adaptively determines the operating voltage according to voltage variation due to manufacturing variability and operates the LSI at the lowest voltage at which its operation is guaranteed, leading to reduced power consumption of the LSI during both operation and standby.
*1:DVFS(Dynamic Voltage Frequency Scaling)
*2:AVS(Adaptive Voltage Scaling)
Standard Cell
In the area of advanced technology, in addition to the standard cell area, routability contributes to the low power consumption of LSIs. We provide our original standard cell that is far superior to that of other companies. In addition, we offer a rich line-up of cells that are effective for achieving low power consumption of the clock system.
Low Power SRAM
An LSI with high-capacity SRAM may have a problem with the power consumption of the SRAM macro. In such cases, power consumption may be reduced by using a multi-mode SRAM. Multi-mode SRAM features a standby mode, sleep mode, and shut-down mode, as well as a normal operation mode. The standby mode allows for the operating power of an SRAM macro to be 0 by stopping the clock operation inside the macro. In sleep mode, leakage power is reduced by deactivating peripheral circuits of the SRAM macro. Power can only be shut down with an SRAM in shutdown mode. The optimization of the SRAM configuration to be used contributes to low power consumption as well. We help customers select the best SRAM from the logic design phase.
| Operating Mode | Function | Effect |
| Normal | To operate RAM normally | - |
| Standby | To stop the SRAM operation | The operating power is 0 |
| Sleep | To retain data | Leakage power is reduced to one-third* |
| Shutdown | To shut down the power with only the SRAM | Leakage power is reduced to one-sixth* |
*:Depends on the SRAM structure
Low Power Design Environment that Fully Adopts UPF/CPS
Socionext offers a total solution that supports power gating, multi power supply, and multi-voltage design through consistent power supply specification management with UPF*1 and CPF*2, RTL simulation for complicated power supply design due to an increased number of integrated IPs, multi power supply verification, and physical design. This solution allows power shutdown verification to be performed based on RTL simulation by managing power supply specifications as separate logical and physical specifications and defining only the logical specification. Verified RTL and the logical specification for the power supply are handed off to physical design, the power supply physical specification that defines the power supply connection is prepared, and then physical design is performed based on these power supply specifications(UPF/CPF). Managing the power supply specification with UPF/CPF in this way and using it through a design flow clarifies the power supply specification and allows for high reliability design.
*1:UPF (Unified Power Format) is a standard specification that defines the Low power design guidelines standardized as IEEE Std. 1801 (http://www.ieee.org/).
*2:CPF (Common Power Format) is a standard specification that defines the Low power design guidelines standardized as Si2 (http://www.si2.org/?page=811).
