Testing SoC is becoming complicated as circuit scale increases, circuit operation becomes faster, and less power is consumed. To resolve this issue, we perform high quality testing by using various types of DFT technology for quality and yield improvement, in order to compressed scan, memory BIST, and boundary scan DFT. DFT Technologies Adopted by Socionext Read More

Front-end Design Kit We offer a development environment using standard EDA tools as a SoC development environment for customers and a tool we created for improving design efficiency as a design kit. The front-end design kit, which is uniquely optimized by Socionext, enables the development of high performance, small chip size, low power LSIs. High Read More

Socionext’s IP macros with their proven track records support customers in advanced SoC development. Functional / Interface Macros *: For details, refer to security subsystems. High Speed Interface Macros Analog Macros  

As the LSI becomes more refined, the number of gates that can be mounted is increasing. In the custom SoC development, the demand to design a chip with more than 100-million gates is increasing. It is also becoming important to fulfill the demands of more complicated designs such as reduction of consumption power. In this Read More

Semiconductor processing technology is down to the deep submicron nodes, and volume production of 28nm semiconductors has already started. Socionext is working with Taiwan Semiconductor Manufacturing Company Limited (TSMC) for manufacturing of 40nm process and further. By the synergetic effect of the world’s best manufacturing capability of TSMC and the quality-control system and design-engineering ability Read More