Testing SoC is becoming complicated as circuit scale increases, circuit operation becomes faster, and less power is consumed. To resolve this issue, we perform high quality testing by using various types of DFT technology for quality and yield improvement, in order to compressed scan, memory BIST, and boundary scan DFT.
DFT Technologies Adopted by Socionext
●At-speed and low power test technologies for quality improvement
- Test using on-chip PLL clocks
- Test that controls power consumption during testing
●Memory redundancy repair process and fault diagnosis technologies for yield improvement
