Whitepaper Series: The Evolution of SerDes Architecture
The advancement of high-speed serial communications has helped expand the Internet and supercharge the growth in the storage, data center, and high-performance computing markets. SerDes (serializer-deserializer) technology advances have driven a 100x increase in serial data rates since 1997.
Our latest whitepaper series discusses the evolution of SerDes Architecture. Download the series to learn why DC-DSP SERDES architecture has several advantages over conventional SERDES architecture, including factors such as better handling of multi-level signaling, superior scaling and robustness, and support for increased serial line rates.
Part I: The Evolution of SerDes Architecture and Advantages of ADC-DSP for High-Speed Serial Communications
The first paper discussed the limitations of NRZ (non-return to zero) data transmission for high-loss channels and presented PAM4 data transmission as a solution to serve the continued increase of serial data rates.
Part II: As Serial Data Rates Continue to Increase, PAM-4 Delivers Significant Advantages
This second section of the series compares NRZ and PAM4 data transmission by simulating data transmission through a 29.8” backplane channel.
Part III: How an ADC-DSP Architecture Can Enable Increased Serial Data Rates
How ADC-DSP SerDes architecture will effectively handle continued increases in serial line rates and mitigate PVT variations in process, voltage, and temperature while reducing package size.
About the Author
Prashant Singh is a Lead Project Engineer at Socionext America. In addition to holding a B.S. degree from the Massachusetts Institute of Technology and a Ph.D. in EE, Prashant possesses over 20 years of experience in optics, microwave circuit design, high-speed test and measurement, and serial communications for optical and copper channels. Prashant specializes in SERDES design and characterization, deep submicron CMOS circuit design, phase-locked loop, high-speed test and measurement, and signal integrity.
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