Socionext to Highlight Leading Edge Technologies in Presentations at Design Automation Conference in San Francisco June 7-11

SUNNYVALE, CA, Jun. 3, 2015 - Socionext Inc., a new leader in advanced custom SoC design technology, will provide a series of presentations about its technology and innovations at the upcoming Design Automation Conference in San Francisco June 7-11.

As part of the DAC session schedule, Masato Tatsuoka of Socionext's Frontend Design Dept. will present "Physically-Aware High Level Synthesis Design Flow." He will propose a new approach on the routing congestion-aware high level synthesis design flow by integrating a HLS tool with physically-aware logic synthesis technology. This approach allows designers to resolve the congestion problems before proceeding to the layout design phase. He has applied this design flow to a large-scale production image processing design. The session is set for June 11 in room 307 at 1:30 pm.

Presentation at Cadence Theater

On June 9 in the Cadence Theater at booth 3515, Mr. Tatsuoka will present "Socionext Inc. High Level Synthesis: A Winning Technology." It will focus on how HLS can be applied to data path IP designs, and also control IP designs, such as DMAC, memory controllers and HEVC Encoder design. The presentation details the benefits of using HLS solutions to achieve first pass silicon in half the time required by traditional RTL design flow methodologies.

To achieve the goal, Socionext has worked with Cadence and introduced three key technologies in the design flow including interface-based design. The Socionext design flow also incorporates Micro-Architecture exploration and physically Aware HLS design flow to reduce risk in the backend. The session is scheduled for 5 pm.

Series of Presentations at Synopsys' Booth and Events

Several other presentations are also set. On June 8, Takuya Yasui, Manager, SoC Design Dept., will present "Transforming Product Deployment with 10X Faster Throughput in ICC Compiler II," at Synopsys' Compiler II Luncheon panel session in the Park Central Hotel starting at 11:30 am. On June 9 at Synopsys' Custom Design Luncheon panel event, Tadafumi Kadota, Senior Engineer of Socionext SoC Design Dept., will present "Adopting Synopsys Custom Designer for 3X TAT Improvement at Advanced Nodes." Both events are in Metropolitan Ballroom I of the hotel at 50 Third St. near Moscone Center.

Socionext will also deliver two presentations at the Synopsys Silicon-to-Software Theater in DAC booth 2133. On June 8 at 10:30 am Paul Little, Director of Technical Marketing, will present "Ever-increasing Bandwidth: High-performance SoC Solutions for Next-Generation Networks." On June 9 at 11 am Rajinder Cheema, Director of Marketing and Applications, High-Performance Business Division, will speak on the same topic.

For official DAC 2015 website and programs, visit www.dac.com.