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Socionext has developed a proprietary architecture based on quantized DNN technology for reducing the parameter and activation bits required for deep learning. The result is improved performance of AI processing along with lower power consumption.
Socionext introduces the new Time-Sensitive Network (TSN) IP for FPGA and ASIC implementation. The IP enables motion controllers and remote I/O used in network communications for control of secured bandwidth and lowering latency.
Introducing the world’s smallest all-digital phase-locked loop (PLL) designed by Tokyo Institute of Technology (Tokyo Tech) and Socionext Inc. enabling new, high-performance system-on-chip (SoC) devices to serve emerging AI, 5G cellular communications, and IoT applications.
Socionext Inc. will exhibit (Hall 3A, Booth 129) at this year’s Embedded World, the leading international fair for embedded systems to be held in Nuremberg, Germany from 25 – 27 February 2020.
Socionext Inc. will feature its advanced SoC designs including 112G SerDes, 120+ GS/s ADC/DAC, PCIe Gen5, high-performance memory, multi-die package design solutions, and AI technology at the annual DesignCon conference, Jan. 28 – 30, at the Santa Clara Convention Center, Booth 1234.
