Socionext Series Highlights Advantages of an ADC-DSP SerDes Architecture for High-Speed Serial Communications

Part I: The Evolution of SerDes Architecture and Advantages of ADC-DSP for High-Speed Serial Communications
The first paper discussed the limitations of NRZ (non-return to zero) data transmission for high-loss channels and presented PAM4 data transmission as a solution to serve the continued increase of serial data rates.

Part II: As Serial Data Rates Continue to Increase, PAM-4 Delivers Significant Advantages
This second section of the series compares NRZ and PAM4 data transmission by simulating data transmission through a 29.8” backplane channel.

Part III: How an ADC-DSP Architecture Can Enable Increased Serial Data Rates
How ADC-DSP SerDes architecture will effectively handle continued increases in serial line rates and mitigate PVT variations in process, voltage, and temperature while reducing package size.

Socionext’s ADC-DSP SerDes architecture has several advantages over a conventional SerDes architecture. In addition to the ability to handle multi-level signaling, such as PAM4, PAM8, and others, using DSP enables complex equalization and clock recovery algorithms. ADC-DSP SerDes greatly improves robustness to PVT variation, and scales well as CMOS dimensions shrink. The ADC-DSP SerDes architecture can also be combined with linear equalization such as CTLE (Continuous-Time Linear Equalizer) and FFE (Feed-Forward Equalizer); thus, providing a practical path forward for continued increase in serial line rates.