We layout customer design with our high-accuracy analysis technology, high performance synthesis, placement, routing, and high speed technology, and low noise design technology.
Physical aware Logic synthesis
Due to the increase in circuit size and routing load caused by the progress of refinement, the gap between the estimate at the time of logic synthesis and layout is widening. At Socionext, we minimize the gap with the layout by taking into account layout information from the logic synthesis step. This allows for early confirmation of timing convergence, thereby shortening the development period.
[Physical aware logic synthesis]
UPF and CPF Support
We support UPF and CPF and perform physical design and physical verification based on power supply specifications for which functional verification is conducted. This enables high design quality to be achieved even for complex low power consumption technologies.
Multiple mode/Corner-aware Optimization
As refinement progresses, the processes, voltage, and temperature conditions (corner conditions) that should be taken into account are increasing. In addition, the number of operation modes is increasing to enhance multifunctionality and secure the reliability of LSIs. In our physical design, placement, routing, and optimization that take into account multiple corner conditions and operation modes are performed. This makes it possible to reduce the iteration of timing optimization due to conflicts between different corners and modes, which shortens the development period.
[Multiple Mode/Corner Optimization]
Power rail analysis/ Crosstalk noise analysis
As refinement progresses and voltages become lower, the delay variation due to an IR drop (voltage drop) in LSIs and crosstalk noise increases. Through high accuracy IR drop and crosstalk noise analysis, we have verified that they do not affect system operations.
[Power rail analysis/ Crosstalk noise analysis]
