Socionext America

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Socionext America, Inc.
Socionext Custom ASIC
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Interface Macros

Socionext provides interface macros that are optimized for various applications to help its customers develop advanced SoCs.

10G-28Gbps SerDes Interface

With a transmission performance of 10Gbps-28Gbps per channel and configuration comprising of multiple channels, our high-performance SerDes macro is appropriate for 100G/200G/400G optical networks or 100G Ethernet systems.

The built-in low-jitter, high-performance PLL enables robust transmission up to 28Gbps per channel.

The interface also supports various standards including OIF-CEI-11G-SR, OIF-CEI-28G-SR, IEEE802.3ba CAUI, and XFI.

28Gbps output waveforms on test chip
28Gbps output waveforms on test chip
28Gbps output waveforms on test chip - Serial - Parallel

  • ×1, ×4 lane configuration.
  • Comprising of Transmitter/Receiver/PLL and capable of bidirectional communication with 1 macro.
  • Up to 112.8Gps per macro (for unidirectional, ×4 configuration).
  • Power-down control on each lane supported.
  • Power-down control for the entire macro supported.
  • Implementing Clock-Data recovery for each Receiver lane.
  • Transmitter Equalization supported.
  • Receiver Equalization supported.
  • Built-in termination resistor in Transmitter/Receiver.
  • Organic flip chip package.
    (0.8mm/1.0mm Ball Pitch, HDBU & SHDBU Package)

USB 3.0 Interface

We have been developing LSIs compatible with the USB3.0 specification since 2009, and have produced more than 10 million units. The USB-IF certified our product as the world's first inter-operability-test compliant device.

In addition, we are developing PHYs for various technologies, and provide high-quality macros that have passed our verification tests, including the compliance test, as a LINK + PHY total package. In our macro lineup, we have combinations of three types of Device / Host / HDC (Host Device Controller) LINK and PHY macros.

Host/HDC Macro

  • Intel xHCI (eXtensible Host Controller Interface) Rev 1.0 supported
  • Integrated DMAC

Device/HDC Macro

  • Endpoint for FIFO (endpoint configuration is changeable)

USB3.0 5.0Gbps Eye Diagram
USB3.0 5.0Gbps Eye Diagram
IP Evaluation Board and Connection Image Interface Macros
IP Evaluation Board and Connection Image

HDMI® Interface

HDMI Application[/caption]HDMI (High-Definition Multimedia Interface) is the industry standard specification for connecting AV equipment such as camcorders, digital cameras, and HDD recorders to DTVs and PC monitors to transmit digital video and audio signals between these devices.

The latest version HDMI-V2.0 is applicable to 4K2K 60 fps (6 Gbps/ch) and HDCP2.2, CEC2.0. We provide controller and PHY macros that are compliant with the HDMI standard.

HDMI Application
HDMI Application

HDMI Macros

  • Non-compressed video transmission
  • Multiple channel (max 32) audio signal transmission
  • Content protection by HDCP2.2
  • Dual viewing
  • 3D image and 4K2K (60 fps) panel
  • Control between devices under Consumer Electronics Control (CEC) 2.0

DDR Interface

Our DDR interface macros range from low and middle speed, forwarding bandwidth to high-speed, forwarding bandwidth or low power, with our various process technologies. Moreover, we support custom SoC development by LSI package board co-design.

DDR Interface Configuration
DDR Interface Configuration

DDR Interface Macros

  • High-speed/high-bandwidth DDR3/DDR4
  • Low-power LPDDR2/LPDDR3/DDR3L
  • DFI compliant (all macro)
  • Compatible with many different DRAM configurations and PKG options, such as Fly-by or PoP, by PHY function (training function).

DDR Interface Design Support (LSI-Package-Board co-design)

  • Timing verification: Verifies timing of all DDR-IF systems including delays between LSI I/O and DRAM
  • Power Integrity: Optimizes the parasitic inductance, resonant frequency, and power supply (PKG, PCB) impedance as the power supply impedance design
  • Signal Integrity: Optimizes the driver strength, terminator resistance, and interconnect topology

PCI Express Interface

The significant improvement of CPU processing capability and the increasing need for large-size data transmission make it  difficult to achieve the expected architecture performance with the existing bus. PCI Express technology is a high-speed interface that enables data transmission of several hundreds of megabytes. Our PCI Express macro is applicable to maximum of 8 GT/s (Gen3). It has passed the PCI Express standard compliance test sponsored by PCI-SIG, and mutual connectivity and reliability with various types of PCI Express interface have been confirmed.

PCI Express Macro Configuration
PCI Express Macro Configuration

PCI Express LINK Macro

  • Compliant with the standard regulation PCI Express Base Specification rev. 3.0
  • Supports lane numbers ×1/ ×4/ ×8.
  • DualMode (RootComplex/Endpoint selectable)
  • AMBA3 I/F selectable for user interface.
  • Integrated DMAC

PCI Express PHY Macro

  • Maximum bit transmission rate 64GT/s
  • Warrants high-speed signal transmission by the de-emphasis function
  • LINK macro interface compliant with the standard regulation PIPE3/PIPE4.

IP Evaluation Board

IP Evaluation Board

SD4.0 Interface

Our Host macro is compliant with the standard SD Version 4.0 specification together with PHY. The PHY, which is compliant with the UHS-II Bus-Interface Specification that was added to the SD4.0 specification, achieves a transfer rate of 312 MB/s. In addition, a controller that is applicable to Legacy Speed IF (maximum 104 MB/s) is mounted, and connection with a conventional SD memory card is supported.

SD4.0 Macro Configuration
SD4.0 Macro Configuration

SD4.0 Host Macro

  • Compliant with SD Host Controller Specifications.
    Part A2 SD Host Controller Standard Specification Version 4.00.
  • Compliant with SDIO Card Specification.
    Part E1 Secure Digital Input/Output (SDIO) Card Specification Version 4.00.
  • 1, 4, 8-bit SD mode supported.
  • Single port supported.
  • Mounted double buffer for transfer (512B, 1 KB, or 2 KB).
  • Data write protect detect function supported.
  • Card-detect function supported.
  • Multiple read/write transfer supported.
  • 1- to 2048-byte transfer-data length supported.
  • Read Wait Option function supported.
  • UHS-I and UHS-II speed mode supported.
  • Re-tuning function supported.
  • Auto CMD23 supported.
  • SDMA, ADMA2 supported.
  • SD-TRAN supported.

UHS-II PHY

  • Compliant with SD Memory Card Specifications.
  • Part1 UHS-II Addendum Version 1.00.
  • Part1 Physical Layer Specification Version 4.00.
  • Maximum transfer speed 312 MB/s.
  • UHS-II 2lane (FD/2L-HD) supported.

MIPI LLI Interface

We provide a LINK macro compatible with LLI Specification Ver. 1.0 and PHY macro compatible with MIPI M-PHY Specification Version 2.0 for MIPI, which is the standard for mobile applications. A major purpose of LLI interfaces is to share memory between chips, which reduces memory costs. In addition, it’s possible to extend functions by connecting with a companion chip, and those chips can communicate with low latency.

MIPI LLI Interface
MIPI LLI Interface

LLI LINK Macro

  • Low-latency traffic class supported
  • Auto SAVE function
  • AXI3.0/AXI4.0 bus interface
  • APB3.0 Register interface

M-PHY Macro

  • For HS transfer mode, supports up to HS-G3
  • For PWM transfer mode, supports from PWM-G0 to G7
  • Supports lane numbers ×2/×4.
  • Maximum transfer rate: 23 Gb/s (×4 lane)